3DRA: Dynamic Data-Driven Reconfigurable Architecture

Specialized accelerators are becoming a standard way to achieve both high-performance and efficient computation. We see this trend extending all areas of computing, from low-power edge-computing systems processors in datacenters. Reconfigurable architectures, such as Coarse-Grained Arrays (CGRAs), attempt find balance between performance energy efficiency by trading off dynamism, flexibility, programmability. Our goal work is new solution that provides the flexibility traditional CPUs, with parallelism CGRA, improve overall efficiency. design, Dynamic Data-Driven Architecture (3DRA), unique, it targets low-latency high-throughput workloads. This architecture implements dynamic dataflow execution model resolves data dependencies at run-time utilizes non-blocking broadcast communication reduces transmission latency single cycle high By employing model, 3DRA eliminates costly mapping algorithms during compilation improves time CGRAs. The achieves up 731 MIPS/mW, 4.43x compared current state-of-the-art CGRA-based accelerators.